1. Field of the Invention
The present invention relates to a method of manufacturing an electronic device. More particularly, it relates to a method of forming a circuit pattern including fine pattern features and fine space defined between the pattern features.
2. Description of the Background Art
As a technique for forming a circuit pattern on an underlying layer (the layer which is ultimately patterned), lithography is generally employed.
According to the lithography technique generally employed, a photoresist provided on the underlying layer is exposed by reduction projection exposure through a reticle which is used with a stepper. As a result, a resist pattern defined on the basis of circuit design is formed in the photoresist, and thereafter, a circuit pattern is formed in the underlying layer using the patterned photoresist as a mask.
In the present invention, a pattern including pattern features for interconnect and the like, and space therebetween, is collectively referred to as a circuit pattern.
As another background technique for forming a finer pattern than that obtained only by the foregoing lithography, pattern shrinkage process has been employed.
The pattern shrinkage process includes shrinkage for shrinking a patterned photoresist (hereinafter referred to as a first shrinkage technique), and shrinkage for shrinking a patterned hard mask (hereinafter referred to as a second shrinkage technique). The details of the first and second shrinkage techniques are given below.
According to the first shrinkage technique, ion implantation, EB (electron beam) curing (hereinafter simply referred to as cure), UV (ultraviolet) cure, high temperature bake (thermal processing), or the like, is performed on the resist pattern of a predetermined configuration, whereby the resist pattern is shrank. Thereafter etching is performed using the shrank pattern as a mask, to form a finer pattern on the underlying layer.
By way of example, a gate electrode of a transistor is formed by the first shrinkage technique, the detail of which will be described.
First, an electronic device on the way to completion is prepared, whose cross section is as illustrated in FIG. 38. The electronic device illustrated in FIG. 38 includes, from the bottom in plan view, an active layer 5, a gate oxide film 6, a gate electrode layer 7, and a photoresist 8 stacked in this order.
Next, as illustrated in FIGS. 39 and 40, a circuit pattern is formed in the photoresist 8 by lithography. FIG. 39 is a plan view of the electronic device at this stage. As shown in FIG. 39, the circuit pattern formed in the photoresist 8 includes pattern features 1 for gate electrode, pattern features 2 for bonding pad (hereinafter referred to as pattern features 2 for pad) connected to the pattern features 1 for gate electrode, space 3 defined between the pattern features 1, space 4 defined between the pattern features 2, and the like. A cross section thereof taken along a cutting line X—X in FIG. 39 is illustrated in FIG. 40.
Thereafter, shrinkage using the process such as ion implantation or EB cure is performed on the patterned photoresist 8, whereby the pattern features 1 and the pattern features 2 constituting the circuit pattern are shrank as shown in FIGS. 41 and 42. FIG. 41 is a plan view of the electronic device at this stage. A cross section thereof taken along a cutting line X′—X′ in FIG. 41 is illustrated in FIG. 42.
Following this, using the shrank photoresist 8 (namely, photoresist including the pattern features 1 and the pattern features 2 after shrinkage) as a mask, etching is performed to define the circuit pattern in the gate electrode layer 7. As a result, gate electrodes 9 and pads 10 are formed. Thereafter the photoresist 8 is removed as shown in FIGS. 43 and 44. FIG. 43 is a plan view of the electronic device at this stage. A cross section thereof taken along a cutting line X″—X″ in FIG. 43 is illustrated in FIG. 44.
As described, according to the first shrinkage technique, the photoresist 8 patterned with the circuit pattern is shrank by the process such as ion implantation. Therefore, the pattern features in the photoresist 8 (namely, the features 1 for gate electrode and the features 2 for pad) are finer than those obtained by lithography. As a result, a finer pattern can be formed in the underlying layer (the gate electrode layer 7). Namely, the finer structures of the gate electrodes 9 and the pads 10 can be obtained.
In addition to the shrinkage of the photoresist 8 as described, the foregoing shrinkage process is further advantageous in that the property of the photoresist 8 is altered, leading to improvement in tolerance thereof to etching (namely, the capability to withstand etching).
Considering the improvement in tolerance to etching in advance, it is possible to define the photoresist 8 to have a small thickness, leading to reduction in aspect ratio. As a result, using etching process, formation of the fine pattern in the underlying layer (in the foregoing example, formation of the thinner gate electrode 9 in the gate electrode layer 7) can be facilitated.
Next, the second shrinkage technique using a hard mask will be described in detail.
In the present invention, a hard mask represents a film provided between an underlying layer to be actually patterned with a circuit pattern and a photoresist, and having a higher etch selectivity relative to the underlying layer.
According to the second shrinkage technique, a hard mask is etched using a previously patterned photoresist as a mask, whereby a circuit pattern is formed in the hard mask. Thereafter isotropic etching is performed to shrink the hard mask. Then the hard mask after shrinkage is used as a mask for etching the underlying layer. As a result, a finer circuit pattern can be formed in the underlying layer.
By way of example, a gate electrode of a transistor is formed by the second shrinkage technique, the detail of which will be described.
First, an electronic device on the way to completion is prepared, whose cross section is as illustrated in FIG. 45. The electronic device illustrated in FIG. 45 includes, from the bottom in plan view, the active layer 5, the gate oxide film 6, the gate electrode layer 7, a hard mask layer 11, and the photoresist 8 stacked in this order.
Next, as illustrated in FIGS. 46 and 47, a circuit pattern is formed in the photoresist 8 by lithography. FIG. 46 is a plan view of the electronic device at this stage. As shown in FIG. 46, the circuit pattern formed in the photoresist 8 includes the pattern features 1 for gate electrode, the pattern features 2 for pad, the space 3 defined between the pattern features 1, the space 4 defined between the pattern features 2, and the like. A cross section thereof taken along a cutting line Y—Y in FIG. 46 is illustrated in FIG. 47.
Thereafter, using the photoresist 8 patterned with the circuit pattern (including the pattern features 1 for gate electrode and the pattern features 2 for pad), etching is performed to define the circuit pattern in the hard mask layer 11. Thereafter the photoresist 8 is removed as shown in FIGS. 48 and 49. FIG. 48 is a plan view of the electronic device at this stage. A cross section thereof taken along a cutting line Y′—Y′ in FIG. 48 is illustrated in FIG. 49.
Next, isotropic etching is performed to shrink the hard mask layer 11 patterned with the circuit pattern, whereby the pattern features 1 and the pattern features 2 constituting the circuit pattern are shrank as illustrated in FIGS. 50 and 51. FIG. 50 is a plan view of the electronic device at this stage. A cross section thereof taken along a cutting line Y″—Y″ in FIG. 50 is illustrated in FIG. 51.
Following this, using the shrank hard mask layer 11 (namely, hard mask layer including the pattern features 1 and the pattern features 2 after shrinkage) as a mask, etching is performed to define the circuit pattern in the gate electrode layer 7. As a result, the gate electrodes 9 and the pads 10 are formed. Thereafter the hard mask layer 11 is removed, whereby the circuit pattern corresponding to that obtained by the first shrinkage technique is formed in the gate electrode layer 7 (FIGS. 43 and 44).
As described, according to the second shrinkage technique, the hard mask layer 11 is added which can be shrank by the simple isotropic etching. Using the hard mask layer 11 after shrinkage as a mask, the gate electrode layer 7 is etched. As a result, the resultant circuit pattern, namely, the pattern including the gate electrodes 9 and the pads 10, is finer than that obtained only by lithography.
The first and second shrinkage techniques are introduced in “Ar ion Implantation into Resist for Etching Resistance Improvement”, A. Yamaguchi et al., pp. 655-664, Proc. of SPIE Vol. 4345 (2001), and Japanese Patent Application Laid-Open No. 2001-308076 (pp. 5-6, FIG. 1), for example.
In exposing the photoresist 8 to form a circuit pattern therein, the lithography process finds difficulty in obtaining high resolution of the fine pattern features 1 and that of the fine spaces 3 and 4 defined between the pattern features under the same conditions.
More particularly, favorable conditions of lithography for obtaining high resolution of the fine pattern features 1 are unfavorable for that of the fine spaces 3 and 4. Conversely, favorable conditions of lithography for high resolution of the fine spaces 3 and 4 are unfavorable for that of the pattern features 1.
For example, illumination conditions for exposure exhibiting excellence in resolution of the fine pattern features 1 are likely to degrade the resolution of the fine spaces 3 and 4. As another example, the material for the photoresist 8 exhibiting excellence in resolution of the fine spaces 3 and 4 are likely to degrade the resolution of the fine pattern features 1.
In view of the above, it is found that there is a trade-off between the resolution of the fine pattern features 1, and that of the fine spaces 3 and 4. When the pattern features 1, and the spaces 3 and 4 are to be simultaneously defined, they cannot have their minimum dimensions at the same time, imposing limitation on the shrinkage of the circuit pattern as a whole.
Further, the shrinkage process encounters the problem as given below.
According to the first or second shrinkage technique, the circuit pattern formed in the photoresist 8 or in the hard mask layer 11 is shrank, whereby the pattern features 1 for gate electrode and the pattern features 2 for pad themselves are shrank. On the contrary, the spaces 3 and 4 defined between the pattern features become wider resulting from the shrinkage of the pattern features. Therefore, integration of the circuit pattern cannot be improved.
As seen from the comparison between FIGS. 48 and 50, or between FIGS. 49 and 51, for example, the shrinkage of the pattern features 2 causes expansion of the space 4 therebetween. That is, the pattern shrinkage process achieves no effect on the shrinkage of the circuit pattern as a whole, leading to no improvement in integration of the circuit pattern.
Making allowance for the amount of shrinkage of the pattern features 2, the space 4 between the features 2 may be designed to be smaller than the one between the features 2 to be subjected to no shrinkage. However, even when the space 4 is designed to have a dimension smaller than its minimum possible dimension at the design stage, it cannot be allocated correctly in the photoresist 8 by the conventional lithography technique due to the foregoing trade-off.